Headquarters USA
Pro Design Electronics Corporation
2107 North First Street / Suite 380
San Jose, CA 95131
USA
Phone: +1 (408) 441-7880
Fax: +1 (408) 441-7885 chipit[at]prodesign-usa[dot]com
Headquarters Europe Pro Design Elecronic GmbH
Albert-Mayer-Strasse 16
D-83052 Bruckmühl
Germany
Phone: +49 (0) 8062-808-0
Fax: +49 (0) 8062-808-404 chipit[at]prodesign-europe[dot]com
CHIPit Iridium Edition V5 The CHIPit Iridium Edition V5, a very cost effective solution for all stages of hardware-assisted verification, gives ASIC & SoC design engineers unprecedented speed and flexibility to verify and debug their designs. With
the newest member of the CHIPit product family, Pro Designs developer
team has succeeded in building a unique high-speed ASIC prototyping
platform for small and medium-sized ASIC designs to accelerate
the verification of complex digital systems. The CHIPit Iridium
Edition combines the advantages of the Platinum and Gold Edition
Pro as well as Pro Designs patented technologies to reach
an impressive conjunction of performance, flexibility, debugging
capability and cost effectiveness.
Highest
Flexibility
The CHIPit Iridium Edition offers a maximum of flexibility.
It is scalable form 1 up to 6 FPGAs and handles design
capacities up to 8 million ASIC gates. The patented
3D Switching Technology enables highest interconnection
flexibility between all FPGAs and assists in adjusting
the connection architecture to the design in the best
way to achieve a maximum system speed performance of up
to 200 MHz. Moreover, the high-speed ASIC prototyping
platform provides up to 2560 free user I/Os on 8 different
extension board sites - 4 on the top side and another
4 on the bottom side of the FPGA board (stack) - to mount
additional standard CHIPit extension boards or additional
application-specific resources like processors, memory
devices, dedicated interfaces, driver circuits etc. to
the system for in-circuit verification.
CHIPit
Iridium Software Package
The CHIPit Iridium Edition comes with a comprehensive software package including CHIPit Manager, Switch Routing Tool, Visibility Tool, HDL Bridge & Signal Tracker, Host Controlled Debug Tool, and an SCE-MI interface for transactional based verification. The CHIPit Manager for complete project administration and system configuration supports design implementation (synthesis/place & route) and handles design partitioning on the prototyping system. The Visibility Tool eases debugging of the design by probing the internal design signals after synthesis/place & route which can then be analyzed for example with tools such as logic analyzers. Other highlights for debugging are 'HDL Bridge' and 'Signal Tracker'.
HDL Bridge is a powerful tool that provides a direct link between a simulation environment (RTL or gate level) to part or the whole DUT (design under test) that is loaded in the CHIPit system. This ensures that the entire design or parts of it run in hardware already in the simulation phase. Combined with Signal Tracker for visualization of the internal signals in the simulator, the designer is provided with an ideal solution for rapid design debugging. The Host-Controlled Debugging Tool allows the user access to all design registers without any synthesis and place & route. The signal values will be stored using VCD files and can be visualized in a wave form viewer.
Key Benefits
Of The CHIPit Iridium Edition V5
Provides up
to 200 MHz system performance ASIC prototyping with
emulation capabilities Scalable platform up to 6 FPGAs 3D Switching Technology
for highest FPGA interconnection flexibility Open connectivity (up
to 2560 free user I/O pins) Interface for C/C++,
Tcl/Tk programming Supports co-simulation,
transaction-based emulation and in-circuit verification
modes Dynamic probe capability
allows interactive debugging Incl. patented UMRBus
Communication System Very robust and transportable
solution Support
for Solaris, Windows and Linux
CHIPit
Iridium Edition V5 Specifications
Capacity
Up
to 8M ASIC gates
Operating
performance
Up to 200
MHz
FPGA
type
-
Xilinx Virtex XC5VLX330
Number
of FPGAs
Scalable
up to 6 FPGAs
Memory
- On-board memories (different options)
- Up to 4 SO-DIMM slots
I/O resources
-
Up to 2560 free user I/O pins, 8 extension board sites
- 6 programmable primary clocks
- 4 additional primary clock inputs
- 7 system-wide clock domains
- Clocks can also be driven by User FPGAs
- Global reset net, controlled from the menu control panel
or by the configuration software
Interconnections
- 640 switchable interconnections per FPGA
- Up to 258 (on one FPGA board) direct interconnections
between the two FPGAs on one board
- 66 switchable interconnections to memory modules
- Up to 2560 connections to 8 PHX-size extension sides