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CHIPit® Platinum Edition
V4 - The new standard for High Speed Verification
The CHIPit Platinum Edition V4,
the next generation in the CHIPit Platinum series, is equipped
with a complete enhanced system architecture based on the
latest Xilinx Virtex 4 FPGA Technology. In addition to that,
the CHIPit V4 system exploits new Software for the System
design implementation and debugging. With the new features
the CHIPit V4 ASIC Prototyping System gives design and verification
engineers unprecedented speed and flexibility to validate
algorithm performance and to verify and debug their ASIC designs.
Besides that it is the best solution, because of the speed
performance, ease of use and size, for the software/firmware
development.
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Innovative
System architecture
The CHIPit Platinum Edition V4 is a scalable FPGA
prototyping system with a minimum of 2.8 M ASIC
gates. The system can be scaled up to the maximum
of 20 M ASIC gates by simply adding boards with
additional capacity. The CHIPit platforms can run
at speeds of up to 200 MHz on board level and up
to 100 MHz on system level. This capacity and performance
gives you the flexibility to verify your design
in new ways which are not possible using logic simulation
or even slower speed “main frame” emulators. Whether
you do architectural verification or algorithmic
designs, whether you have the need for high speed
or complex design verification, the CHIPit Platinum
Edition V4 offers you a growth path for the increasing
complexity. |
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Highest
Flexibility
A further distinctive feature of the CHIPit Platinum Edition
V4 is the “3D Switching Technology”, the name given to
the programmable structure of the high-speed interconnects
between the FPGAs. The patented programmable 3D Switching Technology allows architectural trade-off
optimizations with different design structures of the
SoC design to meet the design challenges for performance
criteria. This technology allows to connect the up to
21 Xilinx Virtex FPGAs XC4VLX100/LX160/LX200 (speedgrade
10/11) in a very flexible manner. The connection topology
can be changed by software at any time as soon as more
than 2 FPGAs are needed to verify a design, which is a
vital requirement with regard to the re-usability of the
system for other projects. |
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Application
areas of the CHIPit Platinum Edition V4
• Algorithm Validation
• IP Validation
• ASIC Prototyping
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Behavioral Prototyping
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Real-time Prototyping
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In-circuit Emulation
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Hardware-software Co-verification
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Firmware/Software Development
Key benefits
of the CHIPit Platinum Edition
V4
• Provides up
to 100MHz System performance on system level
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Emulation and High Speed
Rapid Prototyping in one System
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Scalable System from
3 up 21 FPGAs Xilinx Virtex XC4VLX100/200
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Maximum capacity of 20
M ASIC gates
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Highest FPGA interconnections
flexibility with patented 3D Switching Technology
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Open connectivity (up
to 1920 free user I/O pins)
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Overall extra 192 direct
debug signals + 6 debug clocks
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Transaction based verification
solution (SCE-MI)
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Supports Co-Simulation,
Transaction based Emulation and In-Circuit verification
modes
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Dynamic probes capacity
allow interactive debug
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Incl. patented UMRBus
Communication System (allows test, debugging and
visibility of the design)
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Compact and transportable
solution (e.g. "Prototype" Demonstrator)
• Support
for Solaris, Windows and Linux |
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| CHIPit
Platinum Edition V4 Specifications |
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| Capacity |
From
3.0 M up to 20 M ASIC gates |
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| Operating
performance |
On board level
up to 200MHz, on System level up to 100MHz |
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| FPGA
type |
Xilinx
Virtex XC4VLX100, XC4VLX160, XC4VLX200 (all speedgrades) |
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| Number
of FPGAs |
3, 6, 9,
12, 15, 18 or 21 (scalable) |
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| Memory |
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SDRAM, SSRAM, DDR-SDRAM, etc. over extension boards
- On board memories, different options (SSRAM)
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| I/O resources |
- Up to 1920
free user I/O pins, 6 extension board sections
- Overall extra 192 direct debug signals + 6 debug clocks
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| Onboard
interfaces |
Xilinx JTAG interface for all FPGAs |
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| Software
interfaces |
- Interface
for C/C++, Tcl/Tk programming
- Co-Simulation/Emulation interface
- Interface for transaction-based verification (SCE-MI)
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| System
interface support |
PCI,
PCIX, PCI Express, USB, DVI, Ethernet over extension boards |
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| Communication
interfaces |
- RS422 or
LVDS
- UMRBus
Communication System via PCI card
- Compact flash card |
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| Clocking
schemes |
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8 low skew clock domains
- 1 reset line
- 32 global signals
- Clocks can also be driven by User FPGAs
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| Routing |
- Flexible routable and fixed interconnections (scales with the
number of User FPGAs in the system) |
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| Other features |
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Standalone (bootable system)
- Integrated selftest
- Configuration with embedded system or with Host computer
- LCD monitoring and control panel
- Integrated temperature control |
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| Design
debugging |
- Dynamic
probe capability, In-Circuit mode (Visibility
Tool)
- Dynamic probe capability, Co-Simulation mode (Signal
Tracker Tool) |
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| Software |
-
CHIPit
Configuration Tool
- CHIPit
Manager
- CHIPit
Switch Routing Tool
- CHIPit
Visibility Tool
- CHIPit
HDL Bridge + CHIPit Signal Tracker |
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| Options |
Memory
(SDRAM; SSRAM, DDR-SDRAM), LVDS interface, etc. |
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| Supported
OS |
Linux,
Solaris, Windows |
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| System
Variants |
- Master (Hardware
+ including complete Software + UMRBus)
- Replicator RU (Hardware + Configuration Tools + UMRBus)
- Replicator (Hardware + Configuration Tools) |
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| Dimensions,
weight |
(498mm
x 281mm x 278mm), 20kg |
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| Power
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- 12 V output external
power supply
- Approx. 30A 3.3V power supply
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| More
information |
Download
PDF datasheet |
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| Third
Party Support |
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| FPGA
Synthesis tools |
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DC FPGA™, Synopsys
- Synplify Pro™, Synplicity
- Leonardo™, Mentor Graphics
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Precision Synthesis™, Mentor Graphics
- XST™, Xilinx |
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| FPGA
Partitioning tools |
- APSII, Auspy
- Certify™, Synplicity |
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| ASIC
Synthesis |
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Design Compiler™, Synopsys |
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| HDL
Simulators |
- ModelSim™,
Mentor Graphics
- VCS™, Synopsys
- NC-Sim™, Cadence Design Systems
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H/W Debugging Environment
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Chipscope™, Xilinx
- Identify™, Synplicity |
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