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CHIPit® Platinum Edition
V5 - reaching a new level in High-End ASIC & SoC Prototyping
The CHIPit Platinum Edition V5 is the first ASIC prototyping system that can handle up to 21 Xilinx Virtex-5 FPGAs with a flexible programmable connection topology for a large number of different configurations. In combination with this unique system architecture and the complete new CHIPit Manager Software 4.0 for the design implementation and system configuration the user gets most comfortable and easy to use ASIC Prototyping system on the market.The system can handle complex ASIC and SoC Designs up to 28 M ASIC gates and aims at customers who need a very flexible and high-speed verification solution to shorten the time to market by eliminating costly respins and by providing early prototypes for software development or the end-user.
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| CHIPit
Platinum Edition V5 Specifications |
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| Capacity |
From
4 M up to 28 M ASIC gates |
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| Operating
performance |
On board level
up to 200MHz, on System level up to 100MHz |
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| FPGA
type |
Xilinx
Virtex XC5VLX330 |
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| Number
of FPGAs |
3, 6, 9,
12, 15, 18 or 21 (scalable) |
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| Memory |
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SDRAM, SSRAM, DDR-SDRAM, etc. over extension boards
- On board memory, different options (SSRAM)
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| I/O resources |
- Up to 1920
free user I/O pins, 6 extension board sections
- Overall extra 192 direct debug signals + 6 debug clocks
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| Onboard
interfaces |
-
Xilinx JTAG interface for all FPGAs |
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| Software
interfaces |
- Interface
for C/C++, Tcl/Tk programming
- Co-Simulation/Emulation interface
- Interface for transaction-based verification (SCE-MI)
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| System
interface support |
PCI,
PCIX, PCI Express, USB, DVI, Ethernet and others over extension boards |
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| Communication
interfaces |
- RS422 or
LVDS
- UMRBus
Communication System via PCI card
- Compact flash card |
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| Clocking
schemes |
- Low-skew local and global clock domains
- Built-in clock generator
- Support for external clocks
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| Routing |
- Flexible routable and fixed interconnections (scales with the
number of User FPGAs in the system)
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| Other features |
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Standalone (bootable system)
- Integrated selftest
- Configuration with embedded system or with Host computer
- LCD monitoring and control panel
- Integrated temperature control |
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| Design
debugging |
- Dynamic
probe capability, In-Circuit mode (Visibility
Tool)
- Dynamic probe capability, Co-Simulation mode (Signal
Tracker Tool) |
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| Software |
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CHIPit
Configuration Tool
- CHIPit
Manager
- CHIPit
Switch Routing Tool
- CHIPit
Visibility Tool
- CHIPit
HDL Bridge + CHIPit Signal Tracker |
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| Options |
Memory
(SDRAM; SSRAM, DDR-SDRAM), LVDS interface, etc. |
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| Supported
OS |
Linux, Windows |
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| System
Variants |
- Master (Hardware
+ including complete Software + UMRBus)
- Replicator RU (Hardware + Configuration Tools + UMRBus)
- Replicator (Hardware + Configuration Tools) |
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| Dimensions,
weight |
(498mm
x 281mm x 278mm), 20kg |
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| Power
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- 12 V output external
power supply
- Approx. 30A 3.3V power supply
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| More
information |
Download
PDF datasheet |
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| Third
Party Support |
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| FPGA
Synthesis tools |
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DC FPGA™, Synopsys
- Synplify Pro™, Synplicity
- Leonardo™, Mentor Graphics
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Precision Synthesis™, Mentor Graphics
- XST™, Xilinx |
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| FPGA
Partitioning tools |
- APSII, Auspy
- Certify™, Synplicity |
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| ASIC
Synthesis |
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Design Compiler™, Synopsys |
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| HDL
Simulators |
- ModelSim™,
Mentor Graphics
- VCS™, Synopsys
- NC-Sim™, Cadence Design Systems
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H/W Debugging Environment
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Chipscope™, Xilinx
- Identify™, Synplicity |
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